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? semiconductor msm63182 1/27 general description the msm63182 is a cmos 4-bit microcontroller with built-in 512-dot matrix lcd drivers and operates at 0.9 v (min.). the msm63182 is suitable for applications such as games, toys, watches, etc. which are provided with an lcd display. the msm63182 is an m6318x series mask rom-version product of olms-63k family, which employs oki's original cpu core nx-4/250. the msm63p180 is the one-time-programmable rom version of msm63188, having one-time prom (otp) as internal program memory. the msm63p180 is used to evaluate the software development. features ? rich instruction set 439 instructions transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, rom table reference, external memory transfer, stack operations, flag operations, branch, conditional branch, call/return, control. ? rich selection of addressing modes indirect addressing of four data memory types, with current bank register, extra bank register, hl register and xy register. data memory bank internal direct addressing mode. ? processing speed two clocks per machine cycle, with most instructions executed in one machine cycle. minimum instruction execution time : 61 m s (@ 32.768 khz system clock) 1 m s (@ 2 mhz system clock) ? clock generation circuit low-speed clock : 32.768 khz crystal oscillator high-speed clock : 2 mhz (max.) rc or ceramic oscillator select ? program memory space 4k words basic instruction length is 16 bits/1 word ? data memory space 384 nibbles ? external data memory space 64 kbytes (expandable by using an i/o port) ? semiconductor msm63182 4-bit microcontroller with built-in 512-dot matrix lcd drivers, operating at 0.9 v (min.) e2e0024-38-95 this version: sep. 1998 previous version: mar. 1996
? semiconductor msm63182 2/27 ? stack level call stack level : 8 levels register stack level : 16 levels ? i/o ports input ports: selectable as input with pull-up resistance/input with pull-down resistance/ high-impedance input output ports: selectable as p-channel open drain output/n-channel open drain output/ cmos output/high-impedance output input-output ports: selectable as input with pull-up resistance/input with pull-down resistance/high-impedance input selectable as p-channel open drain output/n-channel open drain output/cmos output/high-impedance output can be interfaced with external peripherals that use a different power supply than this device uses. number of ports: input port : 2 ports 4 bits output port : 4 ports 4 bits input-output port : 3 ports 4 bits ? buzzer function buzzer output : 0.946 to 5.461 khz (adjustable in 15 steps) buzzer output modes : intermittent sound 1, 2; simple sound; continu- ous sound ? lcd driver number of segments : 512 max. (32 seg 16 com) 1/1 to 1/16 duty 1/4 or 1/5 bias (regulator built-in) selectable as all-on mode/all-off mode/power down mode/normal display mode adjustable contrast ? reset function reset through reset pin power-on reset reset by low-speed oscillation halt ? battery check low-voltage supply check criterion voltage : can be selected as 1.05 0.10 v, 1.30 0.15 v, 2.20 0.20 v or 2.80 0.30 v ? power supply backup backup circuit (voltage multiplier) enables operation at 0.9 v minimum
? semiconductor msm63182 3/27 ? timers and counter watchdog timer 1 overflows in 2 sec. 100 hz timer 1 measurable in steps of 1/100 sec. 15-bit time base counter 1 1, 2, 4, 8, 16, 32, 64, and 128 hz signals can be read ? interrupt sources external interrupt : 2 internal interrupt : 6 (watchdog timer interrupt is a nonmask- able interrupt) ? operating voltage when backup used : 0.9 to 2.7 v (low-speed clock operating) 1.2 to 2.7 v (operating frequency: 300 to 500 khz) 1.5 to 2.7 v (operating frequency: 200 khz to 1 mhz) when backup not used : 1.8 to 5.5 v (operating frequency: 300 to 500 khz) 2.2 to 5.5 v (operating frequency: 300 khz to 1 mhz) 2.7 to 5.5 v (operating frequency: 200 khz to 2 mhz) ? package: 128-pin plastic qfp (qfp128-p-1420-0.50-k) : (product name: MSM63182-XXXGS-K) chip : (product name: msm63182-xxx) xxx indicates a code number.
? semiconductor msm63182 4/27 block diagram an asterisk (*) indicates the port secondary function. indicates that the power is supplied to the circuits corresponding to the signal names inside from v ddi (power supply for interface). rom 4kw extmem bus con- trol mie xt0 xt1 osc0 osc1 osc cbr ebr l cg z alu ra a ir instruction decoder ram 384n d0-7* a0-15* rd * wr * nx-4/250 reset rst v ddi pc h y x timing con- trol sp rsp stack cal: 8-level reg: 16-level i/o port p8.0-p8.3 p9.0-p9.3 pa.0-pa.3 1 int v ddh v dd cb1 cb2 p4.0-p4.3 p5.0-p5.3 p6.0-p6.3 p7.0-p7.3 output port data bus tbc 4 int bld int 100hztc 1 back up v ss buzzer bd bdb input port p0.0-p0.3 p1.0-p1.3 lcd & dspr com1-16 seg0-31 tst1 tst tst2 int wdt 1 v dd1 v dd2 v dd3 v dd4 v dd5 c1 c2 v ddl bias int182 1 int
? semiconductor msm63182 5/27 pin configuration (top view) 128-pin plastic qfp note: pins marked as (nc) are no-connection pins which are left open. 1 103 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 (nc) (nc) com16 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 v ddi bdb bd p7.0 p7.1 p7.2 (nc) (nc) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 (nc) (nc) (nc) p7.3 p6.0 p6.1 p6.2 p6.3 p1.0 p1.1 p1.2 p1.3 pa.0 pa.1 pa.2 pa.3 p9.0 p9.1 p9.2 p9.3 p8.0 p8.1 p8.2 p8.3 p0.0 p0.1 p0.2 p0.3 p4.0 p4.1 p4.2 p4.3 p5.0 p5.1 p5.2 (nc) (nc) (nc) (nc) (nc) (nc) seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 (nc) (nc) (nc) 64 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 (nc) (nc) v ss v dd1 v dd2 v dd3 v dd4 v dd5 c1 c2 v ddh cb1 cb2 v dd v ddl osc1 osc0 reset xt1 xt0 tst2 tst1 p5.3 (nc) (nc) (nc)
? semiconductor msm63182 6/27 pad configuration pad layout chip size : 4.44 mm 4.92 mm chip thickness : 350 m m (typ.) coordinate origin : chip center pad hole size : 100 m m 100 m m pad size : 110 m m 110 m m minimum pad pitch : 140 m m note: the chip substrate voltage is v ss . 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 20 22 12 14 16 18 10 p7.2 p7.1 p7.0 bd bdb v ddi com1 com2 com3 com5 com7 com9 com11 com13 com15 com14 com16 com6 com8 com10 com12 com4 23 seg31 25 seg29 24 seg30 30 seg24 27 seg27 29 seg25 26 seg28 28 seg26 31 seg23 33 seg21 32 seg22 38 seg16 35 seg19 37 seg17 34 seg20 36 seg18 43 seg11 40 seg14 42 seg12 39 seg15 41 seg13 44 seg10 46 seg8 45 seg9 51 seg3 48 seg6 50 seg4 47 seg7 49 seg5 54 seg0 53 seg1 52 seg2 55 v ss 60 v dd5 56 v dd1 57 v dd2 58 v dd3 59 v dd4 65 cb2 61 c1 62 c2 63 v ddh 64 cb1 70 reset 66 v dd 67 v ddl 68 osc1 69 osc0 75 p5.3 71 xt1 72 xt0 73 tst2 74 tst1 76 80 85 77 78 79 81 82 83 84 90 86 87 88 89 95 91 92 93 94 100 96 97 98 99 105 101 102 103 104 106 107 p5.2 p4.2 p0.1 p5.1 p5.0 p4.3 p4.1 p4.0 p0.3 p0.2 p8.0 p0.0 p8.3 p8.2 p8.1 pa.3 p9.3 p9.2 p9.1 p9.0 p1.2 pa.2 pa.1 pa.0 p1.3 p6.1 p1.1 p1.0 p6.3 p6.2 p6.0 p7.3 y x
? semiconductor msm63182 7/27 pad coordinates pad no. pad name x (m) y (m) 1 p7.2 C1547 C2265 2 p7.1 C1407 C2265 3 p7.0 C1267 C2265 4 bd C1090 C2265 5 bdb C950 C2265 6v ddi C810 C2265 7 com1 C630 C2265 8 com2 C490 C2265 9 com3 C350 C2265 10 com4 C210 C2265 11 com5 C70 C2265 12 com6 70 C2265 13 com7 210 C2265 14 com8 350 C2265 15 com9 490 C2265 16 com10 630 C2265 17 com11 770 C2265 18 com12 910 C2265 19 com13 1050 C2265 20 com14 1190 C2265 21 com15 1330 C2265 22 com16 1470 C2265 23 seg31 2075 C2170 24 seg30 2075 C2030 25 seg29 2075 C1890 26 seg28 2075 C1750 27 seg27 2075 C1610 28 seg26 2075 C1470 29 seg25 2075 C1330 30 seg24 2075 C1190 31 seg23 2075 C1050 32 seg22 2075 C910 33 seg21 2075 C770 34 seg20 2075 C630 35 seg19 2075 C490 36 seg18 2075 C350 37 seg17 2075 C210 38 seg16 C70 39 seg15 70 40 seg14 210 41 seg13 350 42 seg12 490 43 seg11 630 44 seg10 770 45 seg9 910 46 seg8 1050 47 seg7 1190 48 seg6 1330 49 seg5 1470 50 seg4 1610 51 seg3 1750 52 seg2 1890 53 seg1 2030 54 seg0 2170 55 v ss 1575 2265 56 v dd1 1425 2265 57 v dd2 1275 2265 58 v dd3 1125 2265 59 v dd4 975 2265 60 v dd5 825 2265 61 c1 675 2265 62 c2 525 2265 63 v ddh 375 2265 64 cb1 225 2265 65 cb2 75 2265 66 v dd C75 2265 67 v ddl C225 2265 68 osc1 C375 2265 69 osc0 C525 2265 70 reset C675 2265 71 xt1 C825 2265 72 xt0 C975 2265 73 tst2 C1247 2265 74 tst1 C1387 2265 75 p5.3 C1548 2265 76 p5.2 2170 77 p5.1 2030 78 p4.3 1890 79 p4.2 1750 80 p4.1 1610 81 p4.0 1470 82 p0.3 1330 83 p0.2 1190 84 p0.1 1050 85 p0.0 910 86 p8.3 770 87 p8.2 630 88 p8.1 490 89 p8.0 350 90 p9.3 210 91 p9.2 70 92 p9.1 C70 93 p9.0 C210 94 pa.3 C350 95 pa.2 C490 96 pa.1 C630 97 pa.0 C770 98 p1.3 C910 99 p1.2 C1050 100 p1.1 C1190 101 p1.0 C1330 102 p6.3 C1470 103 p6.2 C1610 104 p6.1 C1750 105 C1890 106 p6.0 C2030 107 p7.3 C2075 C2170 2075 2075 2075 2075 2075 2075 2075 2075 2075 2075 2075 2075 2075 2075 2075 2075 2075 p5.0 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 C2075 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m)
? semiconductor msm63182 8/27 pin descriptions the basic functions of each pin of the msm63182 are described in table 1. a symbol with a slash (/) denotes a pin that has a secondary function. refer to table 2 for secondary functions. for type, "" denotes a power supply pin, "i" an input pin, "o" an output pin, and "i/o" an input- output pin. table 1 pin descriptions (basic functions) function symbol pin type v dd 52 v ss 41 v dd1 42 v dd2 43 v dd3 44 v dd4 45 power supply v dd5 46 c1 47 c2 48 v ddi 110 v ddl 53 v ddh 49 cb1 50 cb2 51 xt0 58 i oscillation xt1 57 o osc0 55 i osc1 54 o test tst1 60 i tst2 59 i reset reset 56 i buzzer bd 108 o bdb 109 o description positive power supply negative power supply power supply pins for lcd bias (internally generated). capacitors (0.1 m f) should be connected between these pins and v ss . capacitor connection pins for lcd bias generation. a capacitor (0.1 m f) should be connected between c1 and c2. positive power supply pin for external interface (power supply for input, output, and input-output ports) positive power supply pin for internal logic (internally generated). a capacitor (0.1 m f) should be connected between this pin and v ss . voltage multiplier pin for power supply backup (internally generated). a capacitor (1.0 m f) should be connected between this pin and v ss . pins to connect a capacitor for voltage multiplier. a capacitor (1.0 m f) should be connected between cb1 and cb2. low-speed clock oscillation pins. a 32.768 khz crystal should be connected between xt0 and xt1, and c g (5 to 25 pf) should be connected between xt0 and v ss . high-speed clock oscillation pins. a ceramic resonator and capacitors (c l0 , c l1 ) or external oscillation resistor (r os ) should be connected to these pins. input pins for testing. a pull-down resistor is internally connected to these pins. the user cannot use these pins. reset input pin. setting this pin to "h" level puts this device into a reset state. then, setting this pin to "l" level starts executing an instruction from address 0000h. a pull-down resistor is internally connected to this pin. buzzer output pin (non-inverted output) buzzer output pin (inverted output)
? semiconductor msm63182 9/27 table 1 pin descriptions (basic functions) (continued) function symbol pin type description p0.0/int5 78 p0.1/int5 77 p0.2/int5 76 p0.3/int5 75 p1.0/int5 94 p1.1/int5 93 p1.2/int5 92 p1.3/int5 91 p4.0/a0 74 p4.1/a1 73 p4.2/a2 72 p4.3/a3 71 p5.0/a4 70 p5.1/a5 69 p5.2/a6 68 p5.3/a7 61 p6.0/a8 98 p6.1/a9 97 p6.2/a10 96 p6.3/a11 95 p7.0/a12 107 p7.1/a13 106 p7.2/a14 105 p7.3/a15 99 port 4-bit input ports. pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. 4-bit output ports. p-channel open drain output, n-channel open drain output, cmos output, or high-impedance output is selectable for each bit. i o i o o o p8.0/ rd 82 p8.1/ wr 81 p8.2 80 p8.3/int4 79 p9.0/d0 86 p9.1/d1 85 p9.2/d2 84 p9.3/d3 83 pa.0/d4 90 pa.1/d5 89 pa.2/d6 88 pa.3/d7 87 4-bit input-output ports. in input mode, pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. in output mode, p-channel open drain output, n-channel open drain output, cmos output, or high-impedance output is selectable for each bit. i/o i/o i/o
? semiconductor msm63182 10/27 table 1 pin descriptions (basic functions) (continued) function symbol pin type description com1 111 com2 112 com3 113 com4 114 com5 115 com6 116 com7 117 com8 118 com9 119 com10 120 com11 121 com12 122 com13 123 com14 124 com15 125 com16 126 seg0 35 seg1 34 seg2 33 seg3 32 seg4 31 seg5 30 seg6 29 seg7 28 seg8 27 seg9 26 seg10 25 seg11 24 seg12 23 seg13 22 seg14 21 seg15 20 seg16 19 seg17 18 seg18 17 seg19 16 seg20 15 seg21 14 seg22 13 seg23 12 seg24 11 o lcd segment signal output pins o lcd common signal output pins lcd
? semiconductor msm63182 11/27 table 1 pin descriptions (basic functions) (continued) function symbol pin type description seg25 10 seg26 9 seg27 8 seg28 7 seg29 6 seg30 5 seg31 4 o lcd segment signal output pins lcd
? semiconductor msm63182 12/27 table 2 shows the secondary functions of each pin of the msm63182. table 2 pin descriptions (secondary functions) function symbol pin type description external interrupt p0.0/int5 78 p0.1/int5 77 p0.2/int5 76 p0.3/int5 75 p1.0/int5 94 p1.1/int5 93 p1.2/int5 92 p1.3/int5 91 external 5 interrupt input pins. the change of input signal level causes an interrupt to occur. the port 0 interrupt enable register (p0ie) and port 1 interrupt enable register (p1ie) enable or disable an interrupt for each bit. i p8.3/int4 79 external 4 interrupt input pin. the change of input signal level causes an interrupt to occur. i
? semiconductor msm63182 13/27 table 2 pin descriptions (secondary functions) (continued) external memory function symbol pin type description p4.0/a0 74 p4.1/a1 73 p4.2/a2 72 p4.3/a3 71 p5.0/a4 70 p5.1/a5 69 p5.2/a6 68 p5.3/a7 61 p6.0/a8 98 p6.1/a9 97 p6.2/a10 96 p6.3/a11 95 p7.0/a12 107 p7.1/a13 106 p7.2/a14 105 p7.3/a15 99 p9.0/d0 86 p9.1/d1 85 p9.2/d2 84 p9.3/d3 83 pa.0/d4 90 pa.1/d5 89 pa.2/d6 88 pa.3/d7 87 p8.0/ rd 82 p8.1/ wr 81 o address output bus for external memory i/o data bus for external memory o read signal output pin for external memory (negative logic) o write signal output pin for external memory (negative logic)
? semiconductor msm63182 14/27 absolute maximum ratings parameter symbol condition rating unit C0.3 to +1.6 power supply voltage 1 ta = 25c v dd1 v C0.3 to +2.9 power supply voltage 2 ta = 25c v dd2 v C0.3 to +4.2 power supply voltage 3 ta = 25c v dd3 v C0.3 to +5.5 power supply voltage 4 ta = 25c v dd4 v C0.3 to +6.8 power supply voltage 5 ta = 25c v dd5 v power supply voltage 6 v dd C0.3 to +6.0 power supply voltage 7 ta = 25c v ddi v C0.3 to +6.0 power supply voltage 8 ta = 25c v ddh v C0.3 to v dd + 0.3 input voltage 1 v dd input, ta = 25c v in1 v C0.3 to v ddi + 0.3 input voltage 2 v ddi input, ta = 25c v in2 v C0.3 to v dd1 + 0.3 output voltage 1 v dd1 output, ta = 25c v out1 v C0.3 to v dd2 + 0.3 output voltage 2 v dd2 output, ta = 25c v out2 v C0.3 to v dd3 + 0.3 output voltage 3 v dd3 output, ta = 25c v out3 v C0.3 to v dd4 + 0.3 output voltage 4 v dd4 output, ta = 25c v out4 v C0.3 to v dd5 + 0.3 output voltage 5 v dd5 output, ta = 25c v out5 v C0.3 to v dd + 0.3 output voltage 6 v dd output, ta = 25c v out6 v C0.3 to v ddi + 0.3 output voltage 7 v ddi output, ta = 25c v out7 v C0.3 to v ddh + 0.3 output voltage 8 v ddh output, ta = 25c v out8 v C55 to +150 storage temperature t stg c (v ss = 0 v) C0.3 to +6.0 power supply voltage 9 ta = 25c v ddl v C0.3 to +6.0 ta = 25c v
? semiconductor msm63182 15/27 recommended operating conditions ? when backup is used v ddi 0.9 to 5.5 v crystal oscillation frequency f xt 30 to 35 khz ceramic oscillation frequency f cm 200k to 1m v dd = 1.5 to 2.7 v parameter symbol condition range unit operating temperature t op C20 to +70 c v dd 0.9 to 2.7 v operating voltage (v ss = 0 v) external rc oscillator resistance r os 50 to 300 v dd = 1.5 to 2.7 v 300k to 500k hz v dd = 1.2 to 2.7 v 100 to 300 k w v dd = 1.2 to 2.7 v v ddi 1.8 to 5.5 v crystal oscillation frequency f xt 30 to 35 khz ceramic oscillation frequency f cm 300k to 1m hz v dd = 2.2 to 5.5 v parameter symbol condition range unit operating temperature t op C20 to +70 c v dd 1.8 to 5.5 v operating voltage (v ss = 0 v) external rc oscillator resistance r os 50 to 300 k w v dd = 2.2 to 5.5 v 200k to 2m v dd = 2.7 to 5.5 v 30 to 300 v dd = 2.7 to 5.5 v 300k to 500k v dd = 1.8 to 5.5 v 100 to 300 v dd = 1.8 to 5.5 v ? when backup is not used
? semiconductor msm63182 16/27 electrical characteristics dc characteristics parameter symbol condition mea- suring circuit unit 1.9 1.8 1.7 v dd2 voltage max. typ. min. v dd2 1/5 bias, 1/4 bias (ta = 25c) v C4 v dd2 voltage temperature deviation d v dd2 mv/c typ.+ 0.3 3/2 v dd2 typ.C 0.3 v dd3 voltage v dd3 1/5 bias v typ.+ 0.4 2 v dd2 typ.C 0.4 v dd4 voltage v dd4 1/5 bias v typ.+ 0.5 5/2 v dd2 typ.C 0.5 v dd5 voltage v dd5 1/5 bias v 1.0 crystal oscillation start voltage v sta oscillation start time: within 5 seconds v 0.9 crystal oscillation hold voltage v hold backup v 5.0 0.1 crystal oscillation stop detect time t stop ms 25 5 external crystal oscillator capacitance c g pf 30 25 20 internal crystal oscillator capacitance c d pf 16 12 8 internal rc oscillator capacitance c os pf 30 external ceramic oscillator capacitance c l0, 1 csa2.00mg (murata mfg.-make) used v dd = 3.0 v pf 0.4 0.0 por voltage v por1 v dd = 1.5 v v 1 0.7 0.0 v dd = 3.0 v v 1.7 backup not used v 2.0 1.5 1.0 v ddl voltage v ddl high-speed clock oscillation stopped v 5.5 1.2 high-speed clock oscillation (v dd = 1.2 to 5.5 v) v v ddh 2.7 2.0 v ddh voltage (backup used) high-speed clock oscillation (ceramic oscillation, 1 mhz) v dd = 1.5 v v high-speed clock oscillation stopped v dd = 1.5 v 3.0 2.8 v (v dd = v ddi = 0.9 to 5.5 v, v ss = 0 v, ta = C20 to +70c unless otherwise specified) typ.+ 0.2 1/2 v dd2 typ.C 0.2 v dd1 voltage v dd1 1/5 bias, 1/4 bias v typ.+ 0.2 v dd2 typ.C 0.2 1/4 bias (connect v dd3 and v dd2 ) typ.+ 0.3 3/2 v dd2 typ.C 0.3 1/4 bias typ.+ 0.4 2 v dd2 typ.C 0.4 1/4 bias 1.5 1.2 non-por voltage v por2 v dd = 1.5 v v 3.0 2.0 v dd = 3.0 v v notes: 1. "t stop " indicates that if the crystal oscillator stops over the value of t stop , the system reset occurs. 2. "por" denotes power on reset. 3. "v por1 " indicates that por occurs when v dd falls from v dd to v por1 and again rises up to v dd . 4. "v por2 " indicates that por does not occur when v dd falls from v dd to v por2 and again rises up to v dd .
? semiconductor msm63182 17/27 parameter symbol condition mea- suring circuit (v dd = v ddi = 1.5 v, v ss = 0 v, ta = C20 to +70c unless otherwise specified) unit max. typ. min. 35 7.0 supply current 1 i dd1 cpu is in halt state. (high-speed clock oscillation stopped) m a 30 5.5 supply current 2 i dd2 cpu is in halt state. lcd is in power down mode. (high-speed clock oscillation stopped) m a 40 24 supply current 3 i dd3 cpu is in operating state. (high-speed clock oscillation stopped) m a 800 600 supply current 4 i dd4 cpu is in operation at high-speed oscillation (rc oscillation, r os = 51 k w ) m a 900 700 supply current 5 i dd5 cpu is in operation at high-speed oscillation (ceramic oscillation, 1 mhz) m a 1 dc characteristics (continued) ? when backup is used ? when backup is not used parameter symbol condition mea- suring circuit (v dd = v ddi = 3.0 v, v ss = 0 v, ta = C20 to +70c unless otherwise specified) unit max. typ. min. 20 3.0 supply current 1 i dd1 cpu is in halt state. (high-speed clock oscillation stopped) m a 18 2.0 supply current 2 i dd2 cpu is in halt state. lcd is in power down mode. (high-speed clock oscillation stopped) m a 20 11 supply current 3 i dd3 cpu is in operating state. (high-speed clock oscillation stopped) m a 600 450 supply current 4 i dd4 cpu is in operation at high-speed oscillation (rc oscillation, r os = 51 k w ) m a 1000 850 supply current 5 i dd5 cpu is in operation at high-speed oscillation (ceramic oscillation, 2 mhz) m a 1
? semiconductor msm63182 18/27 dc characteristics (continued) parameter symbol condition mea- suring circuit (v dd = v ddi = v ddh = 3.0 v, v ss = 0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = C20 to +70c unless otherwise specified) unit max. output current 1 (p4.0 to p4.3) (p5.0 to p5.3) (p6.0 to p6.3) (pa.0 to pa.3) C0.2 ma 2 i oh1 v oh1 = v ddi C 0.5 v C1.0 ma C1.5 ma output current 2 (bd, bdb) output current 4 (osc1) i oh4r v oh4r = v ddh C 0.5 v (rc oscillation) C0.75 ma output leakage (p4.0 to p4.3) (p5.0 to p5.3) (p6.0 to p6.3) (pa.0 to pa.3) i ooh v oh = v ddi 0.3 m a i ool v ol = v ss m a typ. C1.2 C3.0 C4.0 C1.5 min. C2.0 C5.0 C8.0 C2.5 C0.3 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v 2.0 ma i ol1 v ol1 = 0.5 v 5.0 ma 8.0 ma 1.2 3.0 4.0 0.2 1.0 1.5 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v C0.4 ma i oh2 v oh2 = v dd C 0.7 v C2.0 ma C3.0 ma C1.3 C4.0 C5.5 C2.5 C6.0 C9.0 v dd = 1.5 v v dd = 3.0 v v dd = v ddh = 5.0 v 2.5 ma i ol2 v ol2 = 0.7 v 6.0 ma 9.0 ma 1.3 4.0 5.5 0.4 2.0 3.0 v dd = 1.5 v v dd = 3.0 v v dd = v ddh = 5.0 v output current 3 (seg0 to seg31) (com1 to com16) C4 m a i ohm3 m a m a 4 m a i omh3s m a m a v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v C1.0 ma C2.0 C3.5 i ol4r v ol4r = 0.5 v (rc oscillation) 2.5 ma 1.5 0.75 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v 3.5 ma 2.0 1.0 i oh4c v oh4c = v ddh C 0.5 v (ceramic oscillation) C60 m a C180 C300 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v C100 m a C280 C450 i ol4c v ol4c = 0.5 v (ceramic oscillation) 300 m a 120 60 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v 450 m a 200 100 i oh3 v oh3 = v dd5 C 0.2 v (v dd5 level) i ohm3s i oml3 i omh3 m a i oml3s m a i olm3 m a i olm3s m a i ol3 v ohm3 = v dd4 + 0.2 v (v dd4 level) v ohm3s = v dd4 C 0.2 v (v dd4 level) v omh3 = v dd3 + 0.2 v (v dd3 level) v omh3s = v dd3 C 0.2 v (v dd3 level) v oml3 = v dd2 + 0.2 v (v dd2 level) v oml3s = v dd2 C 0.2 v (v dd2 level) v olm3 = v dd1 + 0.2 v (v dd1 level) v olm3s = v dd1 C 0.2 v (v dd1 level) v ol3 = v ss + 0.2 v (v ss level) C4 4 C4 4 C4 4 C4 4
? semiconductor msm63182 19/27 dc characteristics (continued) parameter symbol condition mea- suring circuit (v dd = v ddi = v ddh = 3.0 v, v ss = 0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = C20 to +70c unless otherwise specified) unit max. input current 1 (p0.0 to p0.3) (p1.0 to p1.3) (p8.0 to p8.3) (p9.0 to p9.3) (pa.0 to pa.3) 30 m a 3 i ih1 v ih1 = v ddi (when pulled down) 180 m a 600 m a input current 3 (reset) i ih3 v ih3 = v dd 80 m a typ. 10 90 250 50 min. 2 30 70 10 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v C2 m a i il1 v il1 = v ss (when pulled up) C30 m a C70 m a C10 C90 C250 C30 C180 C600 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v input current 2 (osc0) C30 m a i il2 v il2 = v ss (when pulled up) C150 m a C110 C350 C200 C600 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v v dd = 1.5 v v dd = 3.0 v 600 m a 350 150 i ih1z v ih1 = v ddi (in a high impedance state) 1.0 m a 0.0 i il1z v il1 = v ss (in a high impedance state) 0.0 m a C1.0 i ih2r v ih2r = v ddh (rc oscillation) 1.0 m a 0.0 i il2r v il2r = v ss (rc oscillation) 0.0 m a C1.0 1.0 m a i ih2c v ih2c = v ddh (ceramic oscillation) 3.0 m a 0.5 1.5 0.1 0.75 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v C0.1 m a i il2c v il2c = v ss (ceramic oscillation) C0.75 m a C0.5 C1.5 C1.0 C3.0 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v v dd = v ddh = 5.0 v 2.0 ma 1.0 0.5 i il3 v il3 = v ss 0.0 m a C1.0 input current 4 (tst1, tst2) i ih4 v ih4 = v dd 300 m a 150 50 v dd = 1.5 v v dd = 3.0 v 1.5 ma 1.0 0.5 v dd = v ddh = 5.0 v 4.0 ma 2.5 1.25 i il4 v il4 = v ss 0.0 m a C1.0
? semiconductor msm63182 20/27 dc characteristics (continued) parameter symbol condition mea- suring circuit (v dd = v ddi = v ddh = 3.0 v, v ss = 0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = C20 to +70c unless otherwise specified) unit max. typ. min. input voltage 1 (p0.0 to p0.3) (p1.0 to p1.3) (p8.0 to p8.3) (p9.0 to p9.3) (pa.0 to pa.3) v ddi = 1.5 v 1.2 1.5 v 4 v ih1 v ddi = 3.0 v 2.4 3.0 v v ddi = 5.0 v 4.0 5.0 v input voltage 2 (osc0) d v t2 input pin capacitance (p0.0 to p0.3) (p1.0 to p1.3) (p8.0 to p8.3) (p9.0 to p9.3) (pa.0 to pa.3) c in 5pf hysteresis width 2 (reset, tst1, tst2) 1 v ddi = 1.5 v 0.0 0.3 v v il1 v ddi = 3.0 v 0.0 0.6 v v ddi = 5.0 v 0.0 1.0 v v dd = v ddh = 3.0 v 2.4 3.0 v v ih2 v dd = v ddh = 5.0 v 4.0 5.0 v v dd = v ddh = 3.0 v 0.0 0.6 v v il2 v dd = v ddh = 5.0 v 0.0 1.0 v input voltage 3 (reset, tst1, tst2) v dd = 1.5 v 1.35 1.5 v v ih3 v dd = 3.0 v 2.4 3.0 v v dd = v ddh = 5.0 v 4.0 5.0 v v dd = 1.5 v 0.0 0.15 v v il3 v dd = 3.0 v 0.0 0.6 v v dd = v ddh = 5.0 v 0.0 1.0 v v ddi = 1.5 v 0.05 0.1 0.3 v d v t1 v ddi = 3.0 v 0.2 0.5 1.0 v v ddi = 5.0 v 0.25 1.0 1.5 v hysteresis width 1 (p0.0 to p0.3) (p1.0 to p1.3) (p8.0 to p8.3) (pa.0 to pa.3) v dd = 1.5 v 0.05 0.1 0.3 v v dd = 3.0 v 0.2 0.5 1.0 v v dd = v ddh = 5.0 v 0.25 1.0 1.5 v
? semiconductor msm63182 21/27 measuring circuit 1 measuring circuit 2 v ss a v ih v il *2 v dd v ddi v dd1 v dd2 v dd3 v dd4 v dd5 v ddh input output *3 v ddl *2 input logic circuit to determine the specified measuring conditions. *3 measured at the s p ecified out p ut p ins. c b12 cb1 cb2 c 12 c1 c2 osc0 q osc1 w *1 v ss a v dd v ddi v dd1 v c a v dd2 v c b v dd3 v c c v dd4 v c d v dd5 v c e v ddh v c h xt0 xt1 c g c a , c b , c c , c d , c e , c l , c 12 c b12 , c h c g c l0 c l1 ceramic resonator : 0.1 m f : 1 m f : 15 pf : 30 pf : 30 pf : csa2.00mg (2 mhz) csb1000j (1 mhz) (murata mfg.-make) c l0 c l1 q w q w *1 rc oscillator r os ceramic oscillator ceramic resonator v ddl v c l 32.768 khz crystal
? semiconductor msm63182 22/27 measuring circuit 3 v ss v dd v ddi v dd1 v dd2 v dd3 v dd4 v dd5 v ddh input output a *4 v ddl measuring circuit 4 v ss v ih v il *4 v dd v ddi v dd1 v dd2 v dd3 v dd4 v dd5 v ddh input output *4 measured at the specified input pins. waveform monitoring v ddl
? semiconductor msm63182 23/27 ac characteristics (external memory interface) (v dd = 0.9 to 5.5 v, v ddh = 1.8 to 5.5 v, v ss = 0 v, v ddi = 5.0 v, ta = C20 to +70 c unless otherwise specified) (1) reading from external memory parameter read cycle time rd output delay time output valid time external memory output delay time symbol condition min. typ. max. unit t rc t oe t oha t do 61.0 m s m s m s m s 5.0 5.0 5.0 (a) when cpu operates at 32.768 khz parameter read cycle time rd output delay time output valid time external memory output delay time symbol condition min. typ. max. unit t rc t oe t oha t do 1.0 m s ns ns ns 100 100 150 (b) when cpu operates at 2 mhz (v ddh = 2.7 to 5.5 v) ac characteristics timing ("h" level = 4.0 v, "l" level = 1.0 v) t rc t oe t oha t do address output port setup value port setup value input data port setup value port setup value p7 - p4 (a15 - a0) p8.0 ( rd ) pa, p9 (d7 - d0) movxb obj, [ra] movxb obj, xadr16 s2 s1 s2 s1 s2 s1 system clock 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss )
? semiconductor msm63182 24/27 (2) writing to external memory parameter write cycle time address setup time write time write recovery time symbol condition min. typ. max. unit t wc t as t w t wr 61.0 m s m s m s m s (a) when cpu operates at 32.768 khz data setup time t ds m s data hold time t dh m s 30.5 15.3 15.3 45.8 15.3 parameter write cycle time address setup time write time write recovery time symbol condition min. typ. max. unit t wc t as t w t wr 1.0 m s m s m s m s (b) when cpu operates at 2 mhz (v ddh = 2.7 to 5.5 v) data setup time t ds m s data hold time t dh m s 0.4 0.2 0.2 0.7 0.2 ac characteristics timing ("h" level = 4.0 v, "l" level = 1.0 v) t wc t ds t dh t as address output port setup value port setup value p7 - p4 (a15 - a0) p8.1 ( wr ) pa, p9 (d7 - d0) movxb [ra], obj or movxb xadr16, obj s2 s1 s2 s1 s2 s1 system clock output data port setup value port setup value t w t wr 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss )
? semiconductor msm63182 25/27 application circuits note: v ddi is the power supply pin for the input, output, and input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with power supply backup xt0 com1-16 xt1 v ddh v dd cb1 cb2 v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 bd bdb v ss seg0-31 osc0 osc1 r os p1.3 p1.2 p1.1 p1.0 p0.3 p0.2 p0.1 p0.0 p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 c b12 c v c g c 12 lcd crystal 32.768 khz c h 1.5 v c e c d c c c b c a buzzer ?rc oscillation is selected as high-speed oscillation. ?ports are powered from external memory power source. ?c v is an ic power supply bypass capacitor. ?values of c a , c b , c c , c d , c e , c l , c b12 , c 12 , c h , and c g , are for reference only. v ddi p4-7 p9, pa p8.0 p8.1 sw matrix (8 8) v dd a15-0 d7-0 rd wr v ss external memory (64k 8 bits) 5.0 v v ddl c l open push sw 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 1.0 m f 0.1 m f 0.1 m f 1.0 m f 5 to 25 pf msm63182
? semiconductor msm63182 26/27 note: v ddi is the power supply pin for the input, output, and input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with no power supply backup application circuits (continued) xt0 com1-16 xt1 v ddh v dd v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 bd bdb v ss seg0-31 osc0 osc1 p1.3 p1.2 p1.1 p1.0 p0.3 p0.2 p0.1 p0.0 p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 c v c g c 12 lcd crystal 32.768 khz v dd 5.0 v c e c d c c c b c a buzzer ?ceramic oscillation is selected as high-speed oscillation. ?ports, external memory, and ic share their power supply. ?c v is an ic power supply bypass capacitor. ?values of c a , c b , c c , c d , c e , c l , c 12 , c g , c l0 , and c l1 are for reference only. v ddi p4-7 p9, pa p8.0 p8.1 sw matrix (8 8) v dd a15-0 d7-0 rd wr v ss external memory (64k 8 bits) v dd c l0 30 pf c l1 30 pf ceramic resonator (example: 1 mhz) cb1 cb2 v ddl c l msm63182 open 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f open push sw 5 to 25 pf
? semiconductor msm63182 27/27 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp128-p-1420-0.50-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.19 typ. mirror finish

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